(1) Field of the Invention
The invention relates to digital memory devices and, more particularly, to a highly-integrated, Flash memory and mask ROM array architecture.
(2) Description of the Prior Art
In many electronic applications, it is desirable to combine more than one type of memory on one chip to reduce the cost and to increase the performance. One of the most popular and widely used single-chip combinations is flash memory and ROM.
Referring now to FIG. 1A, a conventional architecture for a memory card with security function is shown. This type of memory card is a passive device. Data may be stored in the card and may be changed during a card read operation. Passive memory cards of this type are widely used for phone card, health insurance card, vending machine card, and car parking card applications. The memory card contains address and security logic 11 to insure secure data exchange, a ROM array 12 to store the security code and data, a Flash or EEPROM array 13 to store the variable data, and I/O logic 14 to perform the data interface.
Referring now to FIG. 1B, a conventional architecture for a microprocessor card, or xe2x80x98smart cardxe2x80x99, is shown. A smart card typically contains an 8-bit to 32-bit MCU or central processing unit (CPU) 15. Some smart cards contain digital signal processors (DSP) to do data storage, management, processing and user interface. The smart card can support one application or multiple applications according to the stored application program run on the MCU. Typically, the smart card software can be freely programmed. Some smart cards even provide an open application program interface to allow new program code to be downloaded. Therefore, the functionality of the smart card is not restricted. One example for the smart card application is the mobile phone card.
The smart card shown contains a CPU 15 to perform the data processing, a RAM array 10 to act as working memory for temporary data storage, a ROM array 12 for storing the operating system, a Flash or EEPROM array 13 to store the variable data, and I/O logic 14 to perform the data interface.
Some of these prior art applications use a flash memory and a ROM on one chip. However, the Flash and ROM arrays are implemented as two discrete arrays. A large amount of chip area is wasted because array access circuitry, signal bus, and data bus must be duplicated for each type of memory array. Thus, it is highly desirable to further integrate the Flash memory and the ROM into one array. This will result in a highly cost-effective system on chip (SOC).
Flash memory is widely used, especially for portable applications, because of its non-volatility and in-system reprogrammability. The basic Flash memory cell structure consists of a control gate, a floating gate, source, and drain. The source and drain are two heavily doped regions on a silicon substrate. A channel exists for electrons to flow from drain to source. The floating gate is located between the control gate and channel. The floating gate is isolated by a thin-tunnel oxide layer and by a dielectric layer. The thin tunnel oxide layer exists between the floating gate and channel. The dielectric material is located between the control and floating gates. The insulators around the floating gate enable electrons to be trapped.
By biasing the control gate, drain, and source with proper voltages, electrons can move in to or out of the floating gate through the tunnel oxide layer. If the electrons move between the channel and floating gate, this operation is considered a xe2x80x98channel-operation.xe2x80x99 An xe2x80x98edge-operationxe2x80x99, in contrast, is defined as electrons moving between the floating gate and the edge of the source or drain.
Increasing the number of electrons raises the cell""s threshold voltage. The threshold voltage is the voltage needed to allow current to flow. The threshold voltage shifts depending on the amount of charged trapped in the floating gate. Therefore, injecting or removing electrons can be used as means to store data. Two different operations are used for changing the Flash memory cell threshold voltage. The erase operation is applied to a large number of cells called a xe2x80x98blockxe2x80x99. Erasing will collectively change the cell threshold voltage to a high or a low threshold voltage. The program operation is performed on a smaller number of cells called a xe2x80x98pagexe2x80x99. Programming changes each cell threshold voltage depending on the desired data. Various mechanisms and technologies are used for erasing and programming different types of Flash memories. In this present invention, the well-known, Fowler-Nordheim (F-N) tunneling mechanism is chosen as an example.
A memory array consists of a plurality of cells arranged in columns and rows. The control gates of the cells in each row are connected to form word lines. The sources and drains of the cells in a column are connected to form source and bit lines. A cell can be read, erased, and programmed in this array by applying proper bias conditions to the word lines and bit lines.
Referring now to FIG. 2, a prior art, NOR-type Flash memory array is illustrated. A small array is shown comprising two word lines 20a and 20b, and two bit lines 21 and 22, and four memory cells M21a, M21b, M22a, and M22b. This type of memory array is suitable for high-speed applications because the bit lines 21 and 22 can be formed using a metal layer having a very short bit line, delay time. Therefore, this type of Flash array is suitable for use in embedded, smart card, or SOC applications as mentioned above.
However, this prior art has several significant disadvantages in embedded applications. Each cell structure M21a contains one transistor and is called a xe2x80x981T cell.xe2x80x99 This type of 1T cell is susceptible to an over-erase condition. In an over-erase condition, the threshold voltage (Vth) of a Flash transistor becomes negative during the erase operation. An over-erased cell will not completely turn OFF when the control gate bias is in the OFF state. The presence of an over-erased Flash cell on a bit line will cause bit line leakage current. Read errors will occur due to this leakage.
To prevent over-erase problems, an additional operation must be performed following the erase operation. A correction operation is performed in order to eliminate the over-erased cells. The correction operation is equivalent to a soft-program operation to increase the Vth of over-erased cells back to a positive range. This correction must be performed on a bit-by-bit basis to prevent overshooting the desired Vth range. Therefore, the correction operation is complex and requires a complicated state machine. In addition, the correction operation significantly slows the re-write cycle of the Flash memory cells and is, therefore, not suitable for the above-described, embedded applications.
An additional problem with the 1T cells of the prior is handling high voltage. During programming, a high voltage signal must be applied to the bit lines. This high voltage will be coupled to the floating gate by the junction-floating gate overlapping area. This cell will turn ON slightly and create bit line current leakage. Each bit line contains a huge number of cells, and, in page-programming mode, a large number of bit lines will be programmed together. Therefore, the lump sum of leakage currents can be substantial. The high voltage signal applied to the bit lines is generated by on-chip, charge pump circuitry. The charge pump circuit is limited in current capability and may not be able to sustain the large leakage current during programming. If the leakage current is too large, the high voltage signal will drop in voltage and cause very slow programming times.
Referring now to FIG. 3, another prior art discloses a two transistor (2T) structure to eliminate the over-erase problem. The 2T cell M31 contains a floating-gate, Flash cell M31a and a select transistor M31b. The select transistor M31b is an enhancement NMOS, having a positive Vth of, for example, +0.7V. The select transistor M31b can be completely turned OFF. Therefore, if the Flash cell M31a is over-erased to a negative Vth, the select transistor M31b will block bit line current such that the overall 2T cell M31 will not conduct leakage current. In addition, because the floating gate cell M31a can be over-erased without causing excessive bit line current, the acceptable Vth range for the floating gate cell M31a is extended from a positive value of, for example, +5V, to a negative value of, for example, xe2x88x921V. A negative Vth results in high current during read operation and is suitable for high-speed embedded applications. In addition, because over-erase is not a concern, a single pulse programming and erasing method can be used. The pulse width is properly chosen to guarantee sufficient erasing or programming to bring the cell Vth to a desired level during the pulse time. A single pulse approach can save significant time and power when compared to conventional erase-and-verify or program-and-verify iterations. These iterations are necessary for the conventional 1T flash cell because of over-erase concerns.
One drawback for the 2T cell is its relatively larger cell size. Compared with the 1T cell, the 2T cell comprises an increase in cell size of between about 40% and 50% due to the extra select transistor. The larger cell size significantly increases the array area and is less cost-effective.
A principal object of the present invention is to provide an effective and manufacturable memory device.
A further object of the present invention is to provide a memory device having a highly integrated array of Flash cells and mask ROM cells.
A yet further object of the present invention is to eliminate over-erase problems by integrating a mask ROM transistor with a Flash transistor to create a novel 2T cell.
Another yet further object of the present invention is to double the memory density by integrating a mask ROM transistor with a Flash transistor.
Another further object of the present invention is to provide a highly integrated Flash cell and mask ROM cell array that is compatible with a range of programming and erasing mechanisms.
Another further object of the present invention to provide a memory device comprising a 2T cell using two Flash transistors.
Another further object of the present invention is to provide a system based on a highly integrated, Flash and mask ROM 2T cell.
In accordance with the objects of this invention, a memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.
Also in accordance with the objects of this invention, a memory cell device is achieved. The memory cell device comprises a first Flash transistor having control gate, flash gate, drain, and source. A second Flash transistor has control gate, flash gate, drain, and source. The first Flash transistor drain is coupled to an array bit line. The second Flash transistor source is coupled to an array source line. The first Flash transistor source is coupled to the second Flash transistor drain.
Also in accordance with the objects of this invention, a device is achieved. The device comprises a memory array comprising a plurality of memory cell devices. The memory cell devices comprise a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. Finally an access controller is included that is capable of accessing the memory array.
Also in accordance with the objects of this invention, a device is achieved comprising a memory array further comprising a plurality of memory cell devices. The memory cell devices comprise a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one of the group consisting of: one Flash transistor and one mask ROM transistor, two Flash transistors, and two mask ROM transistors. Finally, an access controller is included that is capable of accessing the memory array.